Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices

As we reach the limits of current patterning techniques led by 193nm immersion lithography, the focus is on next generation patterning techniques such as Extreme Ultra Violet Lithography (EUVL) and Directed Self Assembly (DSA) to enable 7nm and 5nm technology nodes. Though there have been great strides in materials development for DSA with high χ materials enabling up to 5 nm pitches, DSA still lacks the EDA tool support to enable adoption in layout design and high volume manufacturing. In this paper we plan to alleviate this gap by proposing a framework that encompasses the problems of DSA-aware layout decomposition, grouping and compliance, Guiding Pattern (GP) synthesis, RET and final verification. The above framework will also enumerate the variations of each of the above steps for DSA candidate layers such as vias, fins and metal lines. As components of the above framework, we first propose a family of practical full-chip hybrid multipatterning(MP)/DSA-aware decomposition algorithms capable of using DSA as a relaxation method for reducing coloring conflicts. We then propose a model based GP synthesis algorithm for generating GPs with arbitrary via topologies capable of accurate via placement and also resilient to via phase transition during assembly. The vias assembled using these GPs also show resilience towards post RET process variations. We then perform a Monte-Carlo simulation based feasibility analysis applying DSA to printing of Finfets which shows the pros and cons of using DSA over Self-aligned Double Patterning (SADP) which is the existing technology for printing Fins. We also introduce layout decomposition algorithms for DSA GP and optical trim mask co-optimization.